1. Field of Invention
The present invention pertains to the field of resistive memory cell arrays. More particularly, this invention relates to methods and structure for memory in a resistive memory array for maximizing the signal to noise ratio of the array.
2. Background
A resistive random access memory (RAM) is a cross point type memory array of a planar matrix of spaced memory cells sandwiched between two meshes of conductors running in orthogonal directions above and below the cells. An example is the resistive RAM array 10 shown in FIG. 1. The row conductors 12 running in one direction are referred to as the word lines, and the column conductors 14 extending in a second direction usually perpendicular to the first direction are referred to as the bit lines. The memory cells 16 are usually arranged in a square or rectangular array so that each memory cell unit 16 is connected with one word line 12 and an intersecting bit line 14.
In a resistive RAM array, the resistance of each memory cell has more than one state, and the data in the memory cell is a function of the resistive state of the cell. The resistive memory cells may include one or more magnetic layers, a fuse or anti-fuse, or any element that stores or generates information by affecting the magnitude of the nominal resistance of the element. Other types of resistive elements used in a resistive RAM array include poly-silicon resistors as part of a read-only memory, and floating gate transistors as part of optical memory, imaging devices or floating gate memory devices.
One type of resistive random access memory is a magnetic random access memory (MRAM), in which each memory cell is formed of a plurality of magnetic layers separated by insulating layers. One magnetic layer is called a pinned layer, in which the magnetic orientation is fixed so as not to rotate in the presence of an applied magnetic field in the range of interest. Another magnetic layer is referred to as a sense layer, in which the magnetic orientation is variable between a state aligned with the state of the pinned layer and a state in misalignment with the state of the pinned layer. An insulating tunnel barrier layer sandwiches between the magnetic pinned layer and the magnetic sense layer. This insulating tunnel barrier layer allows quantum mechanical tunneling to occur between the sense layer and the pinned layer. The tunneling is electron spin dependent, causing the resistance of the memory cell, a function of the relative orientations of the magnetizations of the sense layer and the pinned layer. The variations in the junction resistance for the two states of the sense layer determine the data stored in the memory cell. U.S. Pat. No. 6,169,686, granted to Brug et al. on Jan. 2, 2001 discloses such a magnetic memory cell memory.
Referring to FIG. 2, a MRAM memory cell is shown. Memory unit 16 is shown as a three-layer memory cell 20. In each cell 20 a bit of information is stored according to the orientation of a magnetic sense layer 22 of the cell 20. Usually, the cell 20 has two stable magnetic states corresponding to the logic states xe2x80x9c1xe2x80x9d and xe2x80x9c0.xe2x80x9d The two-way arrow 15 on the sense layer 22 shows this binary-state capability. A pinned layer 24 in the cell 20 is separated from the sense layer by a thin insulator 26. Pinned layer 24 has a fixed magnetic orientation, such as shown by the one-way arrow 17 on layer 24. When the magnetic state of the sense layer 22 is oriented in the same direction as the direction of the magnetization of the pinned layer 24, the cell magnetization is referred to as xe2x80x9cparallel.xe2x80x9d Similarly, when the magnetic state of the sense layer 22 is oriented in the direction opposite to the direction of the magnetization of the pinned layer 24, the cell magnetization is referred to as xe2x80x9canti-parallel.xe2x80x9d These orientations correspond to a low resistance state and a high resistance state, respectively.
The magnetic state of a selected memory cell 20 may be changed by applying currents to a word line 12 and a bit line 14 crossing the selected memory cell. The currents produce two orthogonal magnetic fields that, when combined, will switch the magnetic orientation of the selected memory cell 20 between the parallel and anti-parallel states. Other unselected memory cells receive only a magnetic field from either the word line or the bit line crossing the unselected memory cells. The single field is not strong enough to change the magnetic orientation of the unselected cells, so they retain their magnetic orientation.
Referring to FIG. 3, an MRAM memory array 30 is shown. A sense amplifier 32 is connected to the bit line 34 of a selected memory cell 36. A voltage Vr is applied to the word line 38 of the selected memory cell 36, and sense amplifier 32 applies a voltage to the bit line 34 of cell 36. The sense amplifier 32 provides an amplified output 39 reflecting the state of the memory cell 36. The same bit line voltage is applied to all of the bit line 34, effectively biasing all the cells on unselected rows to zero potential. This action isolates the bit line currents from one another, effectively blocking most of the leakage current that might otherwise flow through secondary paths, possibly causing errors in the sensing function of the selected memory cell.
It is understood that the conductors of the word lines and bit lines in the magnetic array all have some amount of resistance to the flow of electricity through the lines. Also, a low resistance state and a high resistance state, corresponding to memory states xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d across the junction of the cross point cell. Although the effects of each such resistance is negligible in itself, the combined effect of these resistances in an array, particularly the conductor resistances, causes some reduction in the available sense current for the sense amplifier to determine the states xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d of the memory cell. If the array becomes too large, the conductor resistances increase because there are more rows and columns. Thus, more current is flowing, and the leakage current through the xe2x80x9csneak pathsxe2x80x9d also increases. Larger current and higher row and column conductor resistance in a large array can cause substantial voltage drops along the word lines and an unequal potential in the bit lines. These effects cause significant reduction in the sense current available to the sense amplifier that can lead to errors in sensing the states of the memory cells.
The problem of errors caused by combined resistances of the conductors becomes worse as the number of memory cells in a memory array are increased. Each conductor must be longer to connect to the increased number of memory cells, resulting is greater line resistance for each conductor. In addition, as arrays become larger, the design of the memory array is scaled smaller to increase the capacity without increasing size of the array. The conductors are made correspondingly thinner and narrower to be able to write data to the memory cells without substantially increasing the write current in the row and column conductors. This decreased thickness of the conductor results in more resistance along each conductor, increasing the possibility of errors or xe2x80x9cnoisexe2x80x9d that interferes with the array output or signal.
The xe2x80x9cmagneto-resistive tunnel junctionxe2x80x9d (MTJ) junction of each memory cell in a MRAM array can also be a factor. As the memory is scaled down in size in order to increase capacity without substantially increasing the array size, there is an increase in MTJ resistance. This increased resistance leads to less tunneling current through the MTJ, thereby reducing the signal current. A xe2x80x9ctunneling currentxe2x80x9d across the junction of each memory cell is a function of the MTJ resistance of each memory cell and can also contribute to the noise of the array. The MTJ resistance across the junction is affected by the material used in the cell and the respective polarizations of the layers on each side of the junction. See Sharma, et al xe2x80x9cSpin-dependent tunneling junctions with AIN and AION barriers,xe2x80x9d 77 Applied Physics Letters, number 14, Oct. 2, 2000.
Accordingly, it is desirable to determine an optimal resistance range of the memory cell and an optimal size of a memory array for a given conductor resistance in order to minimize undesirable error contribution to the output signal. Ability to detect data in the array is measured in terms of signal-to-noise ratio (SNR); higher SNR results in a lower error rate. The SNR is usually measured in decibels (dB). By maintaining the SNR of the array above an acceptable decibel level, the errors contributed by the resistance in the array are maintained at a tolerable level.
Stated another way, it is desirable to determine the MTJ resistance range with respect to memory array size and conductor resistance to minimize the error rate and thus maintain the signal-to-noise ratio above a minimum desirable threshold.
The present invention provides a method of designing a random access (RAM) memory array having resistive elements for optimizing the signal-to-noise ratio for the array. A plurality of memory cells are selected and spaced from each other in a matrix of rows and columns, each memory cell being selected to have a junction resistance values between 0.25 megaohms and 3.60 megaohms. A plurality of conductive row lines are connected between the memory cells in a row and are selected to have a row unit line unit resistance of values between substantially 0.0 ohms and 0.38 ohms. A plurality of conductive column lines are connected between the memory cells in a column and are selected to have a column unit line unit resistance between memory cells, the row unit line unit resistance being approximately equal to the column unit line unit resistance. The values of the memory cell junction resistance are correlated with the values of the row and column unit line resistance so that the signal to noise ratio of the memory array is maintained at 20 decibels or greater.
In another preferred embodiment of the present invention, a resistive random access memory array has selected elements with resistances correlated to maintain a signal-to-noise ratio of 20 decibels or more for the array. A plurality of memory cells are spaced from each other in a matrix of rows and columns, each memory cell being selected to have a junction resistance between 0.80 megaohms and 2.80 megaohms. A plurality of conductive row lines connect between the memory cells in a row are selected to have a determined row unit line resistance between memory cells having values in the range of substantially 0.0 ohms to 0.38 ohms. A plurality of conductive column lines are connected between the memory cells in a column and are selected to have a column unit line resistance having values in the range of substantially 0.0 ohms to 0.38 ohms. The memory cells are selected so that the junction resistance values are correlated with the row or column unit line resistance values, to maintain the signal to noise ratio at 20 decibels or more in the resistive memory array.
Preferably, an optimal design for a 1,024 by 1,024 memory cell array in which the row or column unit line resistance values are selected to be between approximately 0.24 ohms and 0.38 ohms, the range of junction resistance values is selected to be between 0.8 megaohms and 2.8 megaohms. Stated in broad terms, the junction resistance values and column and row unit line resistance values are selected so that the ratio of junction resistance values to row or column unit line resistance values is approximately five million to one.
In accordance with another preferred embodiment of the present invention, a magnetic random access memory (MRAM) array has resistive elements with resistances established to maximize a signal-to-noise ratio of at least 20 decibels for the array. A plurality of magnetic-resistive tunnel junction (MTJ) memory cells are selected and spaced from each other in a square matrix of approximately N rows and N columns, each memory cell being selected to have an MTJ resistance of between 0.25 megaohms and 3.60 megaohms. A plurality of conductive row lines are connected between the memory cells in each row, each row line being selected to have a total row line resistance of N times the row unit resistance between memory cells. A plurality of conductive column lines are connected between the memory cells in each column, each column line being selected to have a total column line resistance of N times the column unit resistance between memory cells. The row and column conductors are selected so that the total row line resistance for each row is approximately equal to the total column line resistance for each column. The MTJ resistance values and row and column conductor resistance values are selected so that the ratio of the MTJ resistance values to the total row or column line resistance values must be greater than approximately five million to N to maintain a signal-to-noise ratio of 20 decibels or more for the memory array. Preferably, where N is equal to approximately 1024, the MTJ resistance values are correlated with the row and column total line resistance values so that the ratio of MTJ resistance to total row or column line resistance is approximately 5,000 or greater.
Other aspects and advantages of the present invention will become apparent from the following detailed description, which in conjunction with the accompanying drawings illustrates by way of example the principles of the present invention.